Mobile wireless devices include receiver circuits for receiving various signals, such as radio frequency (RF) signals, by way of base stations or other transmitters in the wireless network. Because the RF signals often have low power (e.g., low received signal strength), high noise and thus low signal-to-noise ratios, the receiver circuit of a wireless device includes an amplifier, such as a low noise amplifier (LNA), configured to receive and amplify the received RF signals. However, there are circumstances in which the received signal has particularly high received signal strength, for example, when the wireless device is in close proximity to the transmitting base station. When the received signal strength is particularly high, amplification of the RF signal is not necessary and potentially harmful to the receiver circuit. Therefore, the wireless device may also include power control in the amplifier circuit to prevent the receiver circuit from becoming saturated by the high received signal strengths of the RF signals.
One type of power control amplifier circuit includes a bypass switch, which enables a bypass mode parallel to an amplify mode. FIG. 1 is a block diagram of a conventional amplifier circuit 100, which includes amplifier 110 and bypass switch 130 connected in parallel.
Referring to FIG. 1, the amplifier 110 includes common source amplifiers, respectively including first transistor 111 and second transistor 112. A gate of the first transistor 111 is connected to node N 103, which is connected to signal input 132 through capacitor C102 and first bias circuit 151 through resistor R101. A source of the first transistor 111 is connected to a ground voltage and a drain of the first transistor 111 is connected to node N 106 through inductor L101. Node N106 is also connected to voltage source V150, the ground voltage through capacitor C104, and first and second bias circuits 151 and 152. A gate of the second transistor 112 is connected to the drain of the first transistor 111 through capacitor C101. A source of the second transistor 112 is connected to the ground voltage. A drain of the second transistor 112 is connected to node N105, which is connected to node N106 through inductor L102, the second bias circuit 152 through resistor R102, and the signal output 134 through capacitor 103.
The bypass switch 130 is connected between the signal input 132 and the signal output 134. The switch 130 activates (closes) in the bypass mode, so that the RF signal entering the signal input 132 bypasses the amplifier 110. The bypass switch 130 deactivates (opens) in the amplify mode, so that the RF signal entering the signal input 132 is amplified by the amplifier 110. The amplified RF signal is output at the signal output 134.
However, even when operating in the bypass mode, the high signal strength RF signal received at the signal input 132 modulates the gate of the first transistor 111, thus partially turning it on. The first transistor 111 therefore amplifies the input RF signal, and subsequently drives the second transistor 112, which generates unwanted harmonics at the signal output 134 that degrade the overall performance in the bypass mode. Further, parasitics of the amplifier 110 may interfere with circuitry of the bypass switch 130, resulting in a dip in insertion loss occurring within frequency of operation, discussed below.
For example, when the first and second transistors 111 and 112 are in an off state (in the bypass mode), the first parasitic gate-drain capacitance Cgd1 of the first transistor 111 forms a first leakage path (not shown) from the transistor input at its gate to the transistor output at its drain, and the second parasitic gate-drain capacitance Cgd2 of the second transistor 112 likewise forms a second leakage path (not shown) from the transistor input at its gate to the transistor output at its drain. This results in RF signal “leakage” through the deactivated amplifier 110 through the bypass switch 130. Furthermore, the first parasitic gate-drain capacitance Cgd1 in combination with inductor L101 creates a resonance, and a dip in the insertion loss of the bypass switch 130 occurs at this resonance frequency. Depending on the values of the first parasitic gate-drain capacitance Cgd1 and inductor L101, the insertion loss dip may fall within the frequency of operation of the amplifier circuit 100, as shown for example by curve 521 in FIG. 5.
FIG. 2 is a block diagram of a conventional amplifier circuit 200, which includes amplifier 210 having a cascode configuration and bypass switch 230 connected in parallel with the amplifier 210.
For example, the amplifier 210 includes a common source amplifier followed by a common gate amplifier to provide amplification, shown by cascoded first transistor 211 and second transistor 212, respectively. A gate of the first transistor 211 is connected to node N203, which is connected to signal input 232 through capacitor C201 and bias circuit 251 through resistor R201. A source of the first transistor 211 is connected to a ground voltage and a drain of the first transistor 211 is connected to a source of the second transistor 212. A gate of the second transistor 212 is connected to node N205, which is connected to the bias circuit 251 through resistor R202. A drain of the second transistor 212 is connected to signal output 234, which is also connected to node N206 through inductor L201. The node N206 is further connected to the ground voltage through capacitor C204, the bias circuit 251 and voltage source V250. The voltage source V250 must provide a relatively high voltage (e.g., 3.0V), in order to for the amplifier circuit 200 to operate in the cascode configuration.
The bypass switch 230 is connected between the signal input 232 and the signal output 234. The bypass switch 230 activates (closes) in the bypass mode, so that the RF signal entering the signal input 232 bypasses the LNA 210. The switch 230 deactivates (opens) in the amplify mode, so that the RF signal entering the signal input 232 is amplified by the LNA 210. The amplified RF signal is output at the signal output 234.
In the cascode configuration shown in FIG. 2, the first and second transistors are turned off in the bypass mode. However, the gate of the first transistor 211 is modulated by the input signal, generating a drain current that drives the source of the second transistor 212. However, since the source of the second transistor 212 has relatively low impedance, the voltage swing at the drain of the first transistor 211 is minimal, thus reducing harmonic induced by the nonlinear drain-source capacitance (Cds), which improves performance in the bypass mode over a conventional amplifier circuit having common source amplifiers (e.g., amplifier circuit 100 shown in FIG. 1).
However, the cascode configuration of the amplifier circuit 200 has disadvantages. For example, low voltage supply cannot be used since the first and second transistors 211 and 212 are stacked and share a single drain supply. Also, output impedance of the cascode amplifier circuit 200 is very reactive and varies with the frequency of operation, thus making broadband output match very difficult, unless lossy match is employed.